Digital number register



Oct. 17, 1967 Original Filed Dec. .'5, 1962 E. J. TOSCANO DIGITAL NUMBER REGI STER 2 Sheets-Sheet 1 Esteban J. Toscano,

/fvvE/vrofr.

AGENT.

2 Sheets-Sheet Z E. J. TOSCANO DIGITAL NUMBER REGISTER Oct. 17, 1967 Original Filed Dec. 5, 1962 United States Patent O 3,348,156 DIGITAL NUMBER REGISTER Esteban J. Toscano, Los Angeles, Calif., assignor to Hughes Ajrcrat Company, Culver City, Calif., a corporation of Delaware Original application Dec. 3, 1962, Ser. No. 241,630, now Patent No. 3,218,532, dated Nov. 16, 1965. Divided and this application Apr. 15, 1965, Ser. No. 448,524 6 Claims. (Cl. 328-42) ABSTRACT OF THE DISCLQSURE An arrangement for algebraically combiningtwo numbers in a unidirectional counter or register, using bistable elements such as dip-Hops, in which the logical interconnection of the flip-flops permits the insertion of the two numbers in selected groups of flip-flops requiring a total number of pulses for counting out the register equal to the algebraic sum of the two numbers.

This application is la division of application Ser. No. 241,630, now Patent 3,218,532, patented Nov. 16, 1965.

In certain of its aspects this invention is related to a copending patent of the applicant, 3,252,147, issued May 17, 1966, and assigned to the assignee of this invention.

This invention relates generally to unidirectional digital number registers and more particularly to such registers or counters in which numbers may be Valgebra-ically combined.

Unidirectional counters or registers are useful in incremental positioning systems such as found in numerical machine tool controls, for instance, wherein movable platens or tables, spindles, etc., are positioned in one or more axes in accordance with programs deiined in some suitable type of numerical code. Their use minimizes interstage gating with savings in circuit components and in power requirements for the individual stages.

As used in an incremental positioning system of the type disclosed in the copending patent aforesaid, a number read from a fixed program, such as a tape as an instruction for positioning a machine element in one axis, is inserted in the register. If for any reason this'position must be altered, position offset is achieved by generating a second number, independently of the tape and indicative of the magnitude of offset, and inserting this second number in the register. The inal position is the algebraic sum of these two numbers.

An object of this invention is to provide a facility permitting the algebraic summation of two numbers in a one-way counter or register.

The aforesaid and other objects and advantages are accomplished in accordance with one embodiment of this invention in an arrangement utilizing aV count-down counter or counting register which is provided with an additional minimal storage facility which permits the addition of two numbers therein, the rst, in the application described being a number set therein from the program device, and the second being a number set therein in accordance with an adjustment required in the desired position of the part being positioned, with respect to that position which has been programmed.

Other objects and advantages will become apparent from a study of the following specifications when considered in conjunction with the accompanying drawings in which:

FIG. 1 illustrates a typical ip flop of the type which is employed in the counter circuits of this invention.

FIG. 2 is a block diagram specically illustrating a count-down type of counter having a facility for adding Y Patented Oct. 17, 1967 ice two numbers and embodying the principles of this invention; and

FIG. 3 is an electrical circuit schematically depicting a manually operated switch system `for generating discrete electrical signals employed for controlling selected ipflops of the counter of FIG. 2.

A counter of the type described herein provides unidirectional operation, specically a count-down type of operation, and to this end may comprise successive iip iiop Vstages which are arranged so that the lower order ilip ops controls the higher order ilip flops in a special Cascaded nip op arrangement to achieve count-down counter operation. A typical flip flop for such a counter may be of the type illustrated in PIG. 1 herein. This dip flop is described in connection with FIG. 4 of a patent to E. I. Toscano 3,252,147, issued May 1, 1966, and is reproduced herein to facilitate understanding of this invention.

This iiip ilop comprises a pair of transistors Q11 and Q12 of the PNP type which are connected in grounded emitter configuration. The bases and collectors of these transistors are crossconnected in respective voltage divider circuits, the rst of which includes resistors R22, R23 l e and R24, and the second of which includes resistors R25,

R26 and R27. The base of transistor Q11 is connected to the common terminal of resistors R22 and R23 of the rst named voltage divider and the base of transistor Q12 is connected to the common terminal between resistors R25 and R26 of the second named voltage divider. The collector of transistor Q11 is connected to the common terminal between resistors R26 and R27 of the second voltage divider and the collector of transistor Q12 is connected to the common terminal of resistors R23 and R24 of the rst voltage divider.

The respective voltage dividers, during operation of the flip flop, are normally connected between +25 volts and -25 volts, For the purpose of presetting the dip op to one of its two stable states a selected one of the terminals S or R on the voltage divider circuit may be connected momentarily to volts. When -150 volts is connected to terminal S, for instance, the ilip flop is turned on, its l representing electrical state, and when -150 volts is connected to the terminal R the ip ilop is turned od, its 0representing electrical state. While the application of '150 volts is shown only to the terminal S by means of a circuit, yet to be described, it is to be understood that this voltage may be applied to either of the terminals S or R, depending upon the electrical state the ip op is to be set in prior to operation.

Resistors R23 and R26 are respectively shunted by capacitors C6 and C7. Resistors R23, capacitor C6 and resistor R26, capacitor C7, constituting, respectively, the cross-coupling circuits, connect the collector of one transistor to the base of the other transistor to provide fast triggering.

The base circuits of the transistors are provided, respectively, with steering voltage connections to enable switching of the iiip lops from one electrical state to the other without uncertainty. These circuits include resistor R28, diode D14 and resistor R29, diode D15 in series, respectively, between the collector and base of the transistor.

The flip ilop illustrated may be identified las a l-K type of ip op in which the applications of input signals to the J input terminal of the flip flop set the flip op in its l representing or Q electrical state, and applications of input signals to the K input terminal of the ip flop result in setting of the flip op to its 0 representing or electrical state.

J input signals at terminal lp are applied to the base of transistor Q12 through a coupling capacitor C8 and the diode D15. K input signals are applied at the terminal Kp or Kn to the base of transistor Q11. Coupling capa-citor C9 and C11 couple the respective Kp and Kp terminals to the anode of the diode D14 in the base circuit of transistor Q11.

Another input terminal designated SIn is coupled through a coupling capacitor and a diode D13 to the base of transistor Q11.

Clamping diodes D16 and D17 lare provided, respectively, at the collector circuits to apply a clamping voltage of -2 volts as indicated such that when either transistor Q11 or Q12 is not conducting the associated collector circuit will be clamped at about -2 volts.

The on or 1 representing electrical state of this ip op is approximately a -2 volt voltage state at collector terminal Q and the oft or representing electrical state is approximately a zero or ground voltage condition at the terminal Q. When the terminal Q is at -2 volts the terminal is at zero volts. When the terminal Q is at zero volts the terminal Q is at -2 volts. For the flip op to be in its on or 1 representing electrical state transistor Q11 is conducting and transistor Q12 is nonconducting. Under this condition the terminal Q is at -2 volts as determined by the voltage clamp at diode D16. As a consequence of current ilow in the collector circuit of transistor Q11, including resistor R27, the

terminal of the flip op will be at approximately "0 volts, in which case the clamping diode D17 is backbiased. The ip flop is triggered between its two electrical states by cutting off the conducting transistor through application of a positive going voltage pulse to its base. The steering voltage applied by the steering voltage circuits, including resistors R28 and R29, permit control of the ilip op by the simultaneous application of flip flop triggering pulses to both the Jp and Kp input terminals.

FIG. l also illustrates a specific circuit for setting the flip op in its l representing electrical state using the principle of negative base bias to effect switching of transistor Q11. This provision, with reference to the ip flops of the Z and F counters, includes the contacts of a ip op setting relay RS. This relay is provided with a set of normally closed contacts which connects -l-25 volts to the terminal S and a set of normally open contacts which when closed couple -150 volts to the terminal S. For the arrangement illustrated the relay RS is normally deenergized, in which case the terminal S is coupled to 25 volts. The terminal R is indicated as being coupled to 25 volts. In order to set the flip op into its "1 representing electrical state the relay RS is energized. As described in Patent 3,252,147 of E. J. Toscano, supra, energization of relay RS takes place when row 1 of the tape is being read. In this condition -150 volts is coupled through the resistor R22 to the base of flip ilop Q11. This drives the' base of the transistor Q11 negatively with respect to the emitter and transistor conduction takes place. As long as this voltage is applied to the flip ilop the flip .flop is held in this electrical state, even though positive voltage pulses may be applied to the terminals Ip and Kp. With transistor Q11 conducting as described, the output terminal Q is clamped at -2 volts and the output terminal is approximately at zero volts or ground potential and the ip op is in its l representing electrical state.

The details of a count-down type of counter embodying the principles of this invention are illustrated in FIG. 2.

As shown in Patent 3,252,147 to E. I. Toscano, supra, the count-down counter comprises a plurality of cascaded ip ops in which four flip ops are utilized for each of the units, tens, hundreds and thousands level, and two ip flops are in the ten thousands level to provide a total count, expressed as a decimal number of 39,999. The input` pulses which are derived from the position count generator forming a part of the transducer system are applied through the Jp and Kp input terminals of the least significant (first) llip flop of the counter. The output 4. circuit of each flip op is coupled to the Jp and Kp input terminals of the next higher order level of ip op providing triggering of each higher order of ilip ilop as the connected lower order flip op goes from its "0 representing electrical state, in which the output voltage is in the lower of its two Voltage states, to its l representing electrical state in which the output voltage swings from the lower of its two electrical states to the higher of its two electrical states, namely, about -2 volts to ground potential. Thus, at any time a lower orderk ip flop n switches from its "0 or electrical state, a triggering voltage pulse is coupled to the .Ip and Kp input terminals of the next higher order flip op, causing this ip ilop to change from the electrical state it is in to its opposite electrical state, whence the count is transmitted from one flip flop to another to achieve a count-down mode of operation.

This circuit concept for a count-down counter is incorporated in the circuit illustrated in FIG. 2 herein. In FIG. 2 only the units and tens level of a binary coded decimal count-down counter are shown, it being understood that the other levels of this counter may be connected in the manner demonstrated in these two counter levels. To this end, in the units section of the counter the tlip ops F2, F4, F6and F8 represent the standard counter ip op corresponding, for instance, to the flip ops FQxl through FQx4 in Patent 3,252,147 of E. I. Toscano, supra, and the flip ops F11), F12, F14 and F16 will correspond to the flip ilops of the tens level, FQxS through FQx8. In Vthe unitsrrow in FIG. 2 herein control ip flops F1, F3, F5 and F7 are connected ahead of each of the counter flip flops F2, F4, F6 and F8 to provide a control of these counter ip flops for counting purposes, depending upon the amount of correction that is required in the dimension informationthat is being read from the tape. Similarly, flip flops F8, F11, F13 Vand F15fare connected ahead of each of the counter flip ops F10, F12, F14 and F16, respectively, in the tens level of the counter. The control of the counter flip ops by means of the control ip flop is accomplished by means of gating circuits which in the units level of the counter are designated G1, G2, G3 and G4, respectively, and which are arranged to be enabled in the presence of negative output voltages from the control flip ops F1, F3, F5 and F7, respectively. A-similar set of gates couples the flip flops F9, F11, F13 and F15 to the respective counter ip flops in the tens level of the counter. The description of the operation of the Hip flops in the units level of the counter will suflce for both levels.

As illustrated, and with particular reference to the gate G1 (this gate description appliesV to all of the other gates), each gate comprises a pull-down resistor RD having one terminal connected to -25 volts and the other terminal commonly connected to the cathodes of respective gate diodes GD`1 and GD2. At such time as the output voltageV of the terminal of ip flop F1 is at ground potential, the output of the gate is coupled to ground potential. At this time the application of a positive going voltage pulse Pp swinging from some negative voltage, say -2 volts, to ground potential is inhibited at the output of the gate, that is, the voltage pulse does not drive the output ofthe gate above its existing static voltage level at about ground potential. At such time as the output terminal of the flip op F1 is at the lower of its t-wo voltage states, a Voltage pulse coupled to the diode GDI and swinging from some negative potential towards ground potential correspondingly -raises the output of the gating circuit G1. This `output is coupled to both the Jp and Kp input terminals of the llip op F2 which, as described in connection with FIG. 2, causes this flip op to change its electrical state. Thus, at any time the iiip op F1 is in its 0 representing electrical state (=-2 volts), signals Pp are gated by the gate G1 to the inputs Jp and Kp of the iiip flop F2, and at such time as the ilip' flop F1 is in its l representing electrical state, the output of the terminal 'Q is high and the output of the gate G1 is high, which inhibits the pulses Pp at the input terminals Ip and Kp of the flip iiop F2.

Whenever the ip ilop F1 is in its 1 representing electrical state, an input pulse Pp applied to the Kp input terminal thereof switches the flip iiop F1 from its 1 representing electrical state to its Vrepresenting electrical state, thus enabling the gate. Thel second pulse Pp which is applied is now gated to the flip ilop F2, causing this ip flop to change its electrical state. By this expedient the iiip op F1 is eiective in adding one count to the count-down operation. Similar considerations apply with respect to the ip iiops F3, F5 and F7.

The ip ops ofthe counter are weighted 1, 2, 4 and 8 in each of the levels indicated and to achieve binary coded decimal counting the output of the flip iiop F8 is coupled as input to terminals 8in of the iiip flops F4 and F6. Thus, at any time that the iiip tlop F8 goes from its "0 representing electrical state to its l representing electrical state, signals are coupled to the terminals 8in of each of the flip flops F4 and F6 to set these flip flops to their 0 representing electrical states, if they are not already in such electrical states. Thus, in counting, the counter may exist momentarily in the configuration 1111 for the iip flops F2, F4, F6 and F8, respectively, but then, promptly, the iiip ops F4 ad AF6 are switched to their 0 representing electrical states, resulting in a counter coniiguration of the units level representing the decimal number 9. The tens level is similarly connected and thus undergoes similar configuration but is weighted ten times the units level and thus represents the decimal number 90 when in the 1001 conguration.

As described in Patent 3,252,147 of E. J. Toscano, supra, the counter iiip flops F2, F4, F6 and F8 are set by the control afforded by relay RS whenever row 1 of the tape is being read. This applies 150 volts to the S terminal of each iiip flop forcing transistor Q11'to conduct and setting each iiip flop in its 1 representing electrical state. As further described in said Toscano application, the absence of a hole in the tape is effective to turn off any ip flop set in its "1 representing electrical state. Thus, the control from the tape coupled to the Kn input terminal of each ip op is effective to leave this iiip flop in its "1 representing electrical state whenever there is a hole in the tape, or to turn o the flip op with the absence of a hole in the tape. Thus, the counter may be set to a particular electrical conguration representing a particular decimal number corresponding to a dimension indicating the desired position of the part in a particular axis.

At the time the relay RS is energized, each of the iiip ops F1, F3, F5, F7, F9, F11, F13, F15, etc., are also set in their 1 representing electrical states. 1f an offset correction is to be made this correction is then coupled to the input terminals Kn of each of the control or correction iiip ops. The introduction of such a correction may be obtained by means of a switch arrangement of the type illustrated in FIG. 3 and generally designated S. The switch S comprises a knob K which may be set to any one of the ten positions indicated 0 through 9 and is shown in position 7 providing a setting of 0.007 inch. The knob K is mechanically connected to each of the switch sections S1 through S4 and operates the movable switch elements thereof. The switches S1 through S4 are weighted 1, 2, 4 and 84 in correspondence with the weighting of the flip ops in the respective levels of the counter. Each switch is provided with two output terminals designated 1 and "0, respectively. Only the 0 output terminal is utilized in -controlling the control flip flops. These terminals are identified l, Z, S and K4, respectively, which legends are applied in the circuits coupled to the Kn input terminals of the flip iiops F1, F3, F5 and F7 in FIG. 4. The convention adopted here corresponds to that in controlling the iiip ops from the tape, namely,

at any time that a zero is represented in the position of a switch the particular ip op coupled thereto is turned off.

Table I illustrates a typical condition and applies only to the units level ofthe counter. In this table it is assumed that the flip flops FZ, F4, F6 and F8 are initially set to represent the decimal number 9, that is, 1001 reading F2 through F8, which in the units level represents 0.009 inch. The iiip iops F1, F3, F5 and F7 are set to represent the decimal number 7 wherein the iiip ops F1, F3 and F5 are each in their 1 representing electrical states and the flip op F7 is in its "0 representing electrical state, rep- `resenting 0.007 inch in the units level. Thus, prior to the application of a pulse Pp to the input of the counter, the iiip ops occupy the positions indicated in row zero of Table I. Since the flip op F1 is in its 1 representing electrical state, the gate G1 is disabled and consequently the tirst pulse Pp is not coupled to the ip ilop F2 but is coupled only to the Kp input terminal of the ip iiop F1. The positive going voltage excursion at the base of transistor Q11 of this iiip ilop cuts oi transistor Q11 and results in switching on of transistor Q12. The flip iiop F1 now changes its electrical state and the output terminal goes from the higher of its two voltage states to the lower of its two voltage states, namely, about -2 Volts. This enables the gate G1.

TABLE I Pulse No.

The second pulse Pp is now coupled directly through the gate to the terminals Ipand Kp of theY flip flop F2. Flip fiop F2, as shown, was initially in its l representing electrical state and now is switched to its representing electrical state in which condition its output terminal switches from its higher to its lower voltage state. This change in voltage Vin a negative going direction has no effect upon either of the flip flops F3 and F4. As will be seen by reference to Table I, the iiip flop F3 is still in its l representing electrical state.

With the occurrence of the third voltage pulse Pp the flip flop F2 is switched from its 0 representing electrical Ystate to its l representing electrical state. The output voltage at the terminal of the flip ilop F2 now switches in a positive going direction. This positive going voltage excursion is applied to the Kp input terminal of the flip tiop F3 and this iiip flop now changes from its 1 representing electrical state, in which position it was initially set, to its "0 representing electrical state in which the output terminal 'Q is now in the lower of its two voltage states.

The occurrence of the fourth voltage pulse Pp switches the flip iop F2 from its l representing electrical state to its 0 representing electrical state and no further action takes` place. Y l 4 p With the fifth voltage pulse the flip op F2 is now switched from its "0 to its 1 representing electrical state. The positive going excursion of the terminal of the flip op F2 is now coupled through the enabled gate G2 to the input terminals lp and Kp of the iiip op F4 and this Hip iiop, which was initially set its 0 representing electrical state, is now switched to its l representing electrical state. The positive going excursion of the terminal Q' of flip flop F4 which is coupled to the Kp input terminal of the ilip flop F5 switches this flop flop from its l representing electrical state, in which it was initially set, to its 0" representing electrical state and the switching action terminates with this change.

The cycle may now be followed through pulse No. 16, at which the count-down operation is completed, and all of the ip flops are in their "0 representing electrical state. These explanations with respect to the units level of the position counter apply equally to the tens, hundreds, thousands and ten thousands level of the counter of the type described in the Toscano application aforesaid.

Thus, it will be seen that the introduction of the control or correction flip ops in the circuit and the coupling of these iiip ops through suitable gating circuits to the inputs of the counter iiip ops -for the purpose of controlling count-down counting operation provides an arrangement in which two numbers may be conveniently added `in a count-down type of counter with a minimum of equipment.

Although the explanations which have been made hereinabove apply particularly to count-down counters, it will be understood that these principles are generally applicable to a one-way type of counter, whether it be set for count-down operation or count-up operation. For instance, the counter illustrated herein is conveniently changed to a count-up type of counter by the simple expedient of connecting the Q output terminal of each flip op `t0 the Jp, KL, terminal of the next higher level flip' flop in the counter chain so that the occurrence of a pulse Pp at the input Jp, Kp of ip op FZswitching this flip flop, say from its'"1 representing electrical state to `its 0 representing electrical stateis now instrumental in triggering the next higher order flip flop to change its electrical state. The control ip flops F1, F3,- F5, etc., Will be coupled in the manner illustrated to similar gating circuits in order to control the count-up operation. rlp`hus, at any time a control flip flop is switched fromits l state to its 0 state a gate will again be enabled to effect switching of the connected counter flip iiop.

Additionally, a binary coded decimal counter is not needed. For instance, the connections from the output terminals of the flip flops F8 and F16 to the 8In input terminals of the respective pairs of flip flops F4, F6 and F12, F14 may be removed to provide a straight binary circuit.

Further, while all iiip ops are initially set in' their l representing electrical states and then Vselectively turned ou?, if count-up control is provided, they may be initially set to "0 representing electrical state and then only selected control iiip tiops are turned on.

By the arrangement provided herein a simple Aand effec'- tive control of a numericallycontrolled positioning system for providing offset in any degree needed within system limits is achieved. The particular arrangements whereby this may be accomplished, which have been disclosed herein, are subject to modification depending upon the .types of components which are employed, for instance, the type of ip iiop illustrated hereinV is a transistor iiip op and utilizes a negative voltage state to represent the true state of a particular output terminal. Positive voltage states may be employed. Similarly, transistors need not be used in mechanizing the iiip iiops and other elements of the circuit. Vacuum tubes may be employed and other types of switching devices, such as magnetic devices, are equally applicable. The use of a switching circuit of the type illustrated in FIG. 3 illustrates one of several types of devices whichinay be employed and,.agajn, may be modified in accordance with particular needs. I t is, therefore, intended that the foregoing disclosure shall be considered only as illustrative of the principles o'f this invention and not construed in a limiting sense. What is claimed is: 1. A counter, comprising: L a plurality of counter ip olps, each having an input circuit and an output circuit; respective gate circuits coupling the output circuit of each fiipiiop, except the last, to the input circuit of the next higher order flip op; a plurality 'of control nip" iiop's, each, except the lowest order control flip-Hops, having an input circuit coupled to an output circuit o'f a counter flip flop and Y i each having an output circuit coupled to the lgate circuit to which that counter ip flop output circuit is connected;

and means for coupling signals to that gate circuit coupled to the lowest yorder counter ip-op and to the input circuit for the lowest order control ip-op, for operating said counter.

2. A counter, comprising:

.a plurality of counter flip flops, each having an input circuit and an output circuit;

respective gate circuits coupling the output circuit of each ip flop, except the last, to the input circuit of the next higher order flip op;

a plurality of control iiip ops, each having an input circuit coupled to an output circuit of a counter flip iiop and having an output circuit coupled to the 'gate to which that counter ip op output circu'it is connected;

and means coupled to said flip ops for selectively setting said ip fiops in predetermined electrical states.

3. A counter, comprising:

a plurality of counter iiip Hops, each having an input circuit and an output circuit;

respective gate circuits coupling the output circuit of each counter iiip op, except the last, to the input circuit of the next higher order flip op;

a plurality of control ilip flops, each having an input circuit coupled to an output circuit of a counter ilip op .and having an output circuit coupled to the gate to which that counter ip flop output circuit is connected;

means coupled to said counter ip ops and to said control flip lops for setting said ip flops in the same electrical state;

means coupled to said counter flip flops for selectively resetting said counter ip ops;

and means coupled to said control ip ilops for selectively resetting said control flip ops.

4. A counter, comprising:

a plurality of counter flip ops, each having an input circuit and an output circuit; Y

respective gate circuits coupling the output circuit of each ilip Hop, except the last, to the input circuit of the next higher order ip op;

a plurality of control ip ops, each having an input circuit coupled to an output circuit of a counter ip tiop and having an output circuit coupled to the gate to which that counter flip ilop output circuit is connected;

means coupled to said counter flip ops for setting said counter ip ops in the same electrical states;

means coupled to said control iiip ops for setting y each ip ilop, except the last, to the input circuit of the next higher order flip flop;

a plurality of control liip ops, each having an input circuit connected to an output circuit of a counter flip flop and having an output circuit coupled to the gate to which that counter iiip iiop output circuit is connected;

means coupled to said counter iiip flops and to said control Hip flops for setting said ilip ops in their l representing electrical states;

means coupled to said counter ilip ops for selectively resetting selected ip ops to their 0 representing electrical states;

and means coupled to said control ip tiops for selectively resetting selected control ip i'lops to their 0 representing electrical states.

6. A counter, comprising:

a plurality of counter iiip flops, each having an input circuit and an output circuit;

respective gate circuits coupling the output circuit of each ip op, except the last, to the input circuit of the next higher order ip iiop;

a plurality of control flip Hops, each having .an input circuit coupled to an output circuit of a counter iiip iiop and having an output circuit coupled to the gate to which that counter iiip flop output circuit is connected;

means coupled to said counter ip Hops and to said control iiip ilops for setting said flip ops to their 0 representing electrical states;

means coupled to said counter flip flops for selectively resetting selected ip op counters to their l representing electrical states;

and means coupled to said control ip flops for selectively resetting selected control flip flops to their l representing electrical states.

References Cited UNITED STATES PATENTS 3,020,481 2/1962 Hulst 328-42 ARTHUR GAUSS, Primary Examiner.

S. D. MILLER, Assistant Examiner. 

1. A COUNTER, COMPRISING: A PLURALITY OF COUNTER FLIP FLOPS, EACH HAVING AN INPUT CIRCUIT AND AN OUTPUT CIRCUIT; RESPECTIVE GATE CIRCUITS COUPLING THE OUTPUT CIRCUIT OF EACH FLIP FLOP, EXCEPT THE LAST, TO THE INPUT CIRCUIT OF THE NEXT HIGHER ORDER FLIP FLOP; A PLURALITY OF CONTROL FLIP FLOPS, EACH, EXCEPT THE LOWEST ORDER CONTROL FLIP-FLOPS, HAVING AN INPUT CIRCUIT COUPLED TO AN OUTPUT CIRCUIT OF A COUNTER FLIP FLOP AND EACH HAVING AN OUTPUT CIRCUIT COUPLED TO THE GATE CIRCUIT TO WHICH THAT COUNTER FLIP FLOP OUTPUT CIRCUIT IS CONNECTED; AND MEANS FOR COUPLING SIGNALS TO THAT GATE CIRCUIT COUPLED TO THE LOWEST ORDER COUNTER FLIP-FLOP AND TO THE INPUT CIRCUIT FOR THE LOWEST ORDER CONTROL FLIP-FLOP, FOR OPERATING SAID COUNTER. 